The present invention relates to integrated circuit structures and fabrication methods, especially to layout design for DRAM cells. A block diagram of a DRAM memory is shown in FIG. 10.
Background: Layout for Pit-Type DRAM Cell
There are two types of stacked cells in DRAM: the Capacitor Over Bitline (COB) cell and the Capacitor Under Bitline (CUB). The bitline for the CUB cell can be merged with the metal-1 line, which reduces process cost and makes this design attractive for certain applications. However, as sizes shrink and integration increases, e.g. for 1-giga-byte or 4-giga-byte memory, misalignment between various layers, such as the plate layer and the bitline contact, becomes a much larger problem, as will be shown.
FIG. 4 shows the layout of one type of CUB array, this one composed of pit-type capacitors. In the orientation shown in this figure, silicon active areas 108 form elongated ovals separated by dielectric isolation, while gate lines 110 run vertically. Bit-line contacts 124 (BLCTs) are arranged in a diagonal pattern on the active areas, with each BLCT having capacitors 130 on either side.
A cross section along line a-a′ of FIG. 4 reveals a structure like that shown in FIG. 5. In this figure, capacitors 130 are shown overlying gates 110. The capacitors are composed of three layers: a conductive storage node 116, which contacts the underlying wafer through the storage node contact 114, the conductive plate layer 120, which also extends horizontally between capacitors, and capacitor dielectric 118 to separate the conductive layers. The bitline 122 is above the capacitors, while the bitline contact 124 descends through the level of the capacitors to contact the active area at the bitline contact plug 112.
FIG. 6 shows the pattern used on the plate layer 120. As this pattern is compared to the layout shown in FIG. 4, it can be noted that the plate will cover the entire area of the array, except directly around those points where the bit line contacts will be made.
One problem with any layout is the possibility of misalignments between structures. This is illustrated in FIG. 8, which shows the cell of FIG. 5 when a misalignment occurs between the plate and the storage node (see the areas circled). Errors such as this result from the fact that as various layers are patterned, the stepper is aligned to marks which are created for this purpose. These alignment marks become obscured as processing continues, requiring new alignment marks to be formed, with attendant possibilities for errors.
The alignment tree shown in FIG. 7A illustrates the alignment dependencies for this design. In this tree, patterning for the bitline contact (BLCT) plug, the storage node contact (SNCT), and the storage node (SN) are all aligned to marks in the gate layer. Formation of the storage nodes will make it impossible to align further features to the gate level, so the plate level is aligned to marks on the storage node level, while the bitline contact must be aligned to marks on the plate level. As seen in the alignment tree, the further various features are from each other on the alignment tree, the larger can be the potential magnitude of a misalignment between them. For example, in FIG. 7A, there are four layers of possible alignment error between the BLCT and the BLCT plug (BLCT to plate, plate to storage node, storage node to gate, gate to BLCT plug). If a typical 1-layer alignment margin averages 0.052 microns, then statistically a two-layer misalignment will average 0.072, a three-layer misalignment will average 0.88, and a four-layer misalignment will average 0.101 microns. Thus it is very desirable to minimize the alignment relationship between parts of the structure.
Reduced Size Plate Layer
The present application discloses patterning the plate layer to reduce its size and simplify alignment. An important concept underlying the present invention is that, in pit-type DRAM cells, the vertically extended capacitor means that most of the capacitor area is inside the cavity of the storage node. Thus, the contribution to total capacitance by the plate electrode on the field is relatively small. This understanding can be exploited to simplify the alignment relations in pit-type DRAM cells, and hence provide more compact cells and/or higher yield during manufacturing. The plate electrode, according to the preferred embodiment, is not substantially continuous in two orthogonal directions: instead the plate electrode, where it overlies the array or subarray, runs across the array as a series of parallel strips. The bitline contacts fall between the strips, but the alignment of the plate mask is not a critical dimension. Rather than the solid plate with holes shown in FIG. 6, the disclosed process patterns the plate layer as shown in FIG. 1A, in diagonal strips which cover approximately half of each storage node, while the adjacent open area on this level overlies the bitline contact plugs, leaving ample room for the bitline contact to descend, even in the worst misalignment scenario. As seen in the alignment tree of FIG. 7B, the plate layer is no longer in the critical path between the storage node and the bitline contact, reducing the possibility of misalignments. In this example, the greatest misalignment possible is three levels, between the BLCT and the BLCT plug (bitline contact to storage node, storage node to gate, gate to bitline contact plug).
Advantages of the disclosed methods and structures include less risk of misalignments which can cause a defective chip.